It is common practice to use computer-based design tools when constructing mask data for an integrated circuit. Many of these integrated circuit design tools define a metal-routing template that is used to layout low-level cells throughout the integrated circuit. The routing template defines a minimum conductor width and a minimum space between any two adjacent conductors in the integrated circuit. The routing template is used for completing the design of both standard cells and custom cells. Generally, the routing template is defined such that the resulting integrated circuit will meet a set of design constraints including density, anticipated interconnect routing complexity, timing performance, signal integrity and electro migration.
In custom integrated circuits, such as application-specific integrated circuits (ASICs), it is often the case that the set of constraints to which the routing template is optimized will vary across different sub-circuits within the same ASIC design. This is not only true for a single-layer ASIC but applies sub-circuits on each level of a multiple-level ASIC as well. Accordingly, some integrated circuit design tools permit an operator (e.g., a circuit designer) to modify the routing template for a localized portion of the integrated circuit, while maintaining the same general cell pitch (i.e., the distance between the centerlines of respective electrical ground and power supply conductors that provide power to the cell) from cell to cell over the integrated circuit design.
Often, interconnects (i.e., conductors between sub-circuits) between cells using different routing templates need to be made. A circuit designer tasked with using the design tool to route conductors typically uses a high resolution representation of the circuit to locate end points of the various circuit locations that need to be connected. Once, an end point is located, the designer may or may not change the resolution of the representation to route the conductor that will connect the endpoints. When the display resolution is changed, the designer will often have to choose a different resolution (other than the changed or second resolution) to locate a recognizable circuit feature such as the desired end point. This makes the task of locating the end points and routing these and perhaps other interconnects between the cells of the ASIC a slow and tedious process as the designer continuously modifies the display resolution to complete the task.
Thus, improvements in ASIC design tools are required, specifically in the development of systems and methods that enable improved efficiencies in routing interconnects between cells in the ASIC that use disparate routing templates.